18EC734 Dsp Algorithms & Architecture VTU Notes

18EC734 Dsp Algorithms & Architecture VTU CBCS Notes

Here you can download the VTU 2018 Scheme notes, and Study materials of 18EC734 Dsp Algorithms & Architecture of the Electronics and Communications Engineering department.

University Name: Visvesvaraya Technological University (VTU), Belagavi

Branch Name: Electronics and Communication Engineering – ECE

Semester: 7th (4th Year BE)

Subject Code and Subject Name: 18EC734 Dsp Algorithms & Architecture

Scheme of Examination: 2018 Scheme

Marks Distribution: 40 Marks for Continuous Internal Assessment and 60 Marks for Semester end examination

Important Concepts discussed:

1st Module covers “A Digital Signal – Processing System, The Sampling Process, Discrete-Time Sequences, Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT).”

2nd Module covers “Basic Architectural Features, DSP Computational Building Blocks, Bus Architecture and Memory, Data Addressing Capabilities.”

3rd Module covers “Address Generation Unit, Programmability and Program Execution, Speed Issues, Features for External Interfacing.”

4th Module covers “The Q – notation, FIR Filters, IIR Filters, Interpolation and Decimation Filters (one example in each case). Implementation of FFT Algorithms.”

See also  18EC731 Real-Time Systems VTU Notes

5th Module covers “Interfacing Memory and Parallel I/O Peripherals to Programmable DSP Devices.”

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